Globalization of the semiconductor design and manufacturing processes makes integrated circuits (ICs) more vulnerable to malicious activities and alterations than ever before. Reverse engineering, IP (third-party intellectual property) piracy, IC overproduction, and repacking of old ICs have quickly become serious challenges for the IC supply chain. It appears that the global value of counterfeit goods for G20 nations can be now in excess of US $1.7 trillion, and that eliminates or replaces 2.5 million jobs that would otherwise be deployed for legitimate goods. The IC reverse engineering identifies the device technology, structure, and/or its functionality. The objective of the attacker is to successfully reveal a design structure by means of destructive or non-destructive methods. Once the IP netlist is known, it can be illegally sold or used to design other ICs (IC piracy). Also, one can reuse the components extracted from competing products, thus revealing trade secrets. Due to these harmful effects, a pure social loss, and the cost of combating IC counterfeiting and piracy, reverse engineering is considered as one of the most serious threats to the semiconductor industry.
Various defense methods are deployed to hinder reverse engineering and to prevent IP theft. For instance, camouflaging hampers the image processing-based extraction of gate-level netlist by concealing some gates or introducing dummy contacts into the layout. Another technique to impede reverse engineering is logic obfuscation. Encryption blocks (also known as key gates), such as XOR gates, multiplexers and memory elements, are inserted in certain IC locations in order to hide functionality and implementation. A design will function properly only if a correct key drives all of the key gates. Unfortunately, on-chip storage of secret information is inherently prone to a variety of attacks, including side-channel analysis, imaging, and fault analysis.
Physical unclonable functions (PUFs), originally proposed to secure designs through a resilient authentication based on intrinsic semiconductor process variability, can also be used to guide the obfuscation method. In this approach, a device signature may be derived from design-specific attributes, which is clone-resistant as it is virtually impossible to control the manufacturing process variations.
The possibility of hiding logic circuit's functionality carries major implications, however. Obfuscating design logic may introduce unacceptable area, performance, and power overheads. It is thus desirable to explore new techniques that take advantage of circuitry for other purposes to improve the circuit security.